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How Does an FPGA Work?

FPGAs are, at their simplest, a collection of logic gates that you can connect up in almost any way that you wish, to create a circuit. That is an incredibly simplified way of explaining them, however, and it’s the same as telling a child that humans evolved from monkeys, that everything is made from particles, or that the north pole is a fixed position. These are all ‘true enough’, but also massive abstractions.

Main Elements Of An FPGA

In truth, an FPGA board is made up of three main elements – they are look-up tables, the routing matrix, and flip flops.


Look-Up Tables are the things that allow your logic to be put into action. A look-up table has a number of inputs, which then go to an output. The Look-Up table’s power comes from how it can be programmed, so you can dictate what output it should produce for given inputs.

The Look-Up Table has a block of RAM, which is indexed by the inputs. The output of the table will be whatever value is held in that location of the RAM. Let’s imagine a LUT which has just two inputs. That table could have four values (because each input can be a one or a zero:

The inputs could be:

– 00
– 01
– 10
– 11

The table will have four values, and each value could have a different output. The output could be set to anything, and you can have multiple gates interacting in complex ways. To make an AND gate, you would set the first three inputs to produce an output of 0, and the 11 input to produce an output of 1.

In most commercial FPGAs you will have 5 or even 6 input LUTs for complex applications.

The output of the LUTs can be connected to a flip-flop, and a group of flip-flops is called a slice. Many FPGAs have thousands of LUTs, and over 1,000 slices.

Complex Logic Blocks

The next ‘level’ of block in an FPGA is the Complex Logic Block. Each CLB in an FPGA is made up of two slices, and each CLB connects to a switch matrix which connects that block to the rest of the device. The switch matrix then allows the inputs and outputs to be connected to a general routing matrix, similar to how the output from one LUT can then be connected to the input of another LUT.

FPGA routing can be quite complex, especially when you are dealing with thousands upon thousands of gates. To complicate things further, there are some special routing options, such as clock routing resources, which are used if you need a clock feature – because you want the clock signal to be distributed evenly for consistent flip flop performance. The general routing resources are likely to have propagation delays, but the clock-specific resources should, in theory, perform at a consistent pace. It is these resources which limit the performance of FPGAs compared to ASIC designs, and mean that they consume considerably more power than such designs too. To know more visit the website at

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